The SN74BCT29854 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted from the B to A bus with its corresponding parity bit, the parity-error (
) output will indicate whether or not an error in the B data has occurred. The output-enable (
, 
) inputs can be used to disable the device so that the buses are effectively isolated.
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector parity-error () flag. can be either passed, sampled, stored, or cleared from the latch using the latch-enable (
) and clear (
) control inputs. When both and are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition which gives the designer more system diagnostic capability. The SN74BCT29854 provides inverting logic.
The SN74BCT29854 is characterized for operation from 0°C to 70°C.
| Supply voltage (min) (V) | 4.5 |
| Supply voltage (max) (V) | 5.5 |
| Number of channels | 9 |
| IOL (max) (mA) | 48 |
| IOH (max) (mA) | -24 |
| Input type | TTL |
| Output type | TTL |
| Features | High speed (tpd 10-50ns) |
| Technology family | BCT |
| Rating | Catalog |
| Operating temperature range (°C) | 0 to 70 |
| SOIC (DW) | 24 | 159.65 mm² 15.5 x 10.3 |
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