These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation allows for maximum flexibility in timing.
The ’HC623 devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic levels at the output-enable (OEAB and OEBA) inputs.
OEAB and OEBA disable the device so that the buses are effectively isolated. The dual-enable configuration gives the transceivers the capability to store data by simultaneously enabling OEAB and OEBA. Each output reinforces its input in this transceiver configuration. When both OEAB and OEBA are enabled and all other data sources to the two sets of bus lines are in the high-impedance state, both sets of bus lines (16 total) remain at their last states. The 8-bit codes appearing on the two sets of buses are identical.
| Supply voltage (min) (V) | 2 |
| Supply voltage (max) (V) | 6 |
| Number of channels | 8 |
| IOL (max) (mA) | 7.8 |
| IOH (max) (mA) | -7.8 |
| Input type | CMOS |
| Output type | CMOS |
| Features | Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode |
| Technology family | HC |
| Rating | Catalog |
| Operating temperature range (°C) | -40 to 85 |
| PDIP (N) | 20 | 228.702 mm² 24.33 x 9.4 |
| SOIC (DW) | 20 | 131.84 mm² 12.8 x 10.3 |
| SOP (NS) | 20 | 98.28 mm² 12.6 x 7.8 |
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