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The TPS766 is a low-dropout (LDO) linear voltage regulator that supports an input voltage range from 2.5 V to 16 V (new chip) and up to 250 mA of load current. For the new chip, the supported output range is from 1.2 V to 12 V (fixed version) or from 0.8 V to 14.6 V (adjustable version).

The input voltage range is up to 16 V (new chip), which makes the device a good choice for operating from transformer secondary windings and regulated rails (such as 10 V or 12 V). Additionally, the wide output voltage range allows the device to generate the bias voltage for silicon carbide (SiC) gate drivers and microphones, as well as power microcontrollers (MCUs) and processors.

Wide bandwidth PSRR performance is greater than 70 dB at 1 kHz and 46 dB at 1 MHz (new chip), which helps attenuate the switching frequency of an upstream DC/DC converter and minimizes post regulator filtering. The new chip supports internal soft-start circuit mechanism that reduces inrush current during start-up, thus allowing for smaller input capacitance.

The legacy chip supports constant quiescent current across the complete load current range (typically 35 µA for the full range of output current, 0 mA to 250 mA).

The TPS766 LDO also features a sleep mode, where applying a TTL high signal to EN (enable) shuts down the regulator. In disabled mode, the quiescent current for the legacy chip is less than 1 µA (typ) and the quiescent current for the new chip is approximately 1.6 µA (typ).

Power-good (PG) is an active-high output that can be used to implement a power-on reset or a low-battery indicator.

For the fixed-output version, The TPS766 provides an output range of 1.5 V to 5.0 V (legacy chip) and 1.2 V to 12 V (new chip). For the adjustable version, output voltage can programmed over the range of 1.25 V to 5.5 V (legacy chip) and 0.8 V to 14.6 V (new chip). The TPS766 is available in an 8-pin SOIC package.