This 10-bit FET bus switch is designed for 3-V to 3.6-V VCC operation and SSTL_2 output-enable (OE) input levels.
When OE is low, the 10-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the two ports. There are 10-k
pulldown resistors to ground on the B port.
The FET switch on-state resistance is designed to replace the series terminating resistor in the SSTL_2 data path.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.
| Configuration | 1 |
| Number of channels | 10 |
| Power supply voltage - single (V) | 3.3 |
| Protocols | Analog |
| Ron (typ) (Ω) | 5 |
| ON-state leakage current (max) (µA) | 1000 |
| Bandwidth (MHz) | 200 |
| Operating temperature range (°C) | -40 to 85 |
| Features | Powered-off protection |
| Input/output continuous current (max) (mA) | 48 |
| Rating | Catalog |
| Drain supply voltage (max) (V) | 3.6 |
| Supply voltage (max) (V) | 3.6 |
| SOIC (DW) | 24 | 159.65 mm² 15.5 x 10.3 |
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