The SN74CBTLV3125 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE) input is high.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
| Configuration | 1 |
| Number of channels | 4 |
| Power supply voltage - single (V) | 2.5, 3.3 |
| Protocols | Analog, I2C, I2S, JTAG, RGMII, SPI, TDM, UART |
| Ron (typ) (Ω) | 5 |
| ON-state leakage current (max) (µA) | 1 |
| Bandwidth (MHz) | 200 |
| Operating temperature range (°C) | -40 to 85 |
| Input/output continuous current (max) (mA) | 128 |
| Rating | Catalog |
| Drain supply voltage (max) (V) | 3.6 |
| Supply voltage (max) (V) | 3.6 |
| SOIC (D) | 14 | 51.9 mm² 8.65 x 6 |
| SSOP (DBQ) | 16 | 29.4 mm² 4.9 x 6 |
| TSSOP (PW) | 14 | 32 mm² 5 x 6.4 |
| TVSOP (DGV) | 14 | 23.04 mm² 3.6 x 6.4 |
| VQFN (RGY) | 14 | 12.25 mm² 3.5 x 3.5 |
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