LMK04100系列介绍资料

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LMK04100

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具有级联 PLL 的精密时钟调节器时钟抖动消除器

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The LMK04100 family of precision clock conditioners provides jitter cleaning, clock multiplication and distribution without the need for high-performance VCXO modules.

When connected to a recovered system reference clock and a VCXO, the device generates 5 low jitter clocks in LVCMOS, LVDS, or LVPECL formats.

Cascaded PLLatinum PLL Architecture
- PLL1Redundant Reference Inputs Loss of Signal
  DetectionAutomatic and Manual Selection of
  Reference Clock Input
- PLL2Phase Detector Rate up to 100 MHzInput
  Frequency-DoublerIntegrated VCO
Outputs
- LVPECL/2VPECL, LVDS, and
  LVCMOS Formats
- Support Clock Rates up to 1080 MHz
- Five Dedicated Channel Divider Blocks
- Common Output Frequencies Supported:
  30.72 MHz, 61.44 MHz, 62.5 MHz,
  74.25 MHz, 75 MHz, 77.76 MHz, 100 MHz,
  106.25 MHz, 125 MHz, 122.88 MHz,
  150 MHz, 155.52 MHz, 156.25 MHz, 159.375 MHz,
  187.5 MHz, 200 MHz,
  212.5 MHz, 245.76 MHz, 250 MHz, 311.04 MHz,
  312.5 MHz, 368.64 MHz,
  491.52 MHz, 622.08 MHz, 625 MHz, 983.04 MHz
MICROWIRE (SPI) Programming Interface
Industrial Temperature Range: –40 to 85 °C
3.15 V to 3.45 V Operation
Package: 48 Pin WQFN (7.0 × 7.0 × 0.8 mm)

Function	Cascaded PLLs
Number of outputs	7
RMS jitter (fs)	150
Output frequency (min) (MHz)	0.29
Output frequency (max) (MHz)	1296
Input type	LVCMOS, LVDS, LVPECL
Output type	LVCMOS, LVPECL
Supply voltage (min) (V)	3.15
Supply voltage (max) (V)	3.45
Features	Loss of signal detection
Rating	Catalog
Operating temperature range (°C)	-40 to 85
Number of input channels	2

WQFN (RHS)

49 mm² 7 x 7

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LMK04100

具有级联 PLL 的精密时钟调节器时钟抖动消除器

4000-306-326