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Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.
The clock conditioner comes in a 48-pin LLP package and is footprint compatible with other clocking devices in the same family.
| Function | Clock generator |
| Number of outputs | 4 |
| Output frequency (max) (MHz) | 800 |
| Core supply voltage (V) | 3.3 |
| Output supply voltage (V) | 3.3 |
| Input type | LVCMOS, LVPECL |
| Output type | LVPECL |
| Operating temperature range (°C) | -40 to 85 |
| Features | Integrated integer-N PLL, uWire |
| Rating | Catalog |
| WQFN (RHS) | 48 | 49 mm² 7 x 7 |