CDCP1803系列介绍资料

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CDCP1803

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具有可编程分频器的 1:3 LVPECL 时钟缓冲器

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The CDCP1803 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0] with minimum skew for clock distribution. The CDCP1803 is specifically designed for driving 50-Ω transmission lines.

The CDCP1803 has three control terminals, S0, S1, and S2, to select different output mode settings; see for details. The CDCP1803 is characterized for operation from –40°C to 85°C. For use in single-ended driver applications, the CDCP1803 also provides a VBB output terminal that can be directly connected to the unused input as a common-mode voltage reference.

Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs
Programmable Output Divider for Two LVPECL Outputs
Low-Output Skew 15 ps (Typical)
V_CC Range 3 V–3.6 V
Signaling Rate Up to 800-MHz LVPECL
Differential Input Stage for Wide Common-Mode Range
Provides VBB Bias Voltage Output for Single-Ended Input Signals
Receiver Input Threshold ±75 mV
24-Terminal QFN Package (4 mm × 4 mm)
Accepts Any Differential Signaling:
LVDS, HSTL, CML, VML, SSTL-2, and
Single-Ended: LVTTL/LVCMOS

Function	Differential, Fanout
Additive RMS jitter (typ) (fs)	150
Output frequency (max) (MHz)	800
Number of outputs	3
Output supply voltage (V)	3.3
Core supply voltage (V)	3.3
Output skew (ps)	15
Features	Pin programmable
Operating temperature range (°C)	-40 to 85
Rating	Catalog
Output type	LVPECL
Input type	LVPECL

VQFN (RGE)

16 mm² 4 x 4

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CDCP1803

具有可编程分频器的 1:3 LVPECL 时钟缓冲器

4000-306-326