The CDC351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution. The output-enable (OE) input disables the outputs to a high-impedance state. The CDC351 operates at nominal 3.3-V VCC.
The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended for customer use and should be connected to GND.
EPIC-IIB is a trademark of Texas Instruments Incorporated.
| Function | Single-ended |
| Output frequency (max) (MHz) | 100 |
| Number of outputs | 10 |
| Output supply voltage (V) | 3.3 |
| Core supply voltage (V) | 3.3 |
| Output skew (ps) | 0.6 |
| Features | Pin control |
| Operating temperature range (°C) | -40 to 85 |
| Rating | Catalog |
| Output type | LVTTL |
| Input type | LVTTL |
| SOIC (DW) | 24 | 159.65 mm² 15.5 x 10.3 |
| SSOP (DB) | 24 | 63.96 mm² 8.2 x 7.8 |
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