h1_key

The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, CLKIN) to nine pairs of differential clock (Y, Y) outputs with minimum skew for clock distribution. It is specifically designed for driving 50- transmission lines.

When the output-enable (OE) is low, the nine differential outputs switch at the same frequency as the differential clock inputs. When OE is high, the nine differential outputs are in static states (Y outputs are in the low state, Y outputs are in the high state).

The V_REF output can be strapped to the CLKIN input for a single-ended CLKIN input.

The CDC111 is characterized for operation from 0°C to 70°C.