The SN65LVEP11 is a differential 1:2 PECL/ECL fanout buffer. The device includes circuitry to maintain known logic levels when the inputs are in an open condition. Single-ended clock input operation is limited to VCC ≥ 3 V in PECL mode, or VEE ≤ 3 V in NECL mode. The device is housed in an industry-standard SOIC-8 package and is also available in TSSOP-8 package option.
| Function | Translator |
| Protocols | ECL, PECL |
| Number of transmitters | 2 |
| Number of receivers | 1 |
| Supply voltage (V) | 2.5, 3.3, 3.8 |
| Signaling rate (MBits) | 6000 |
| Input signal | ECL, PECL |
| Output signal | ECL, PECL |
| Rating | Catalog |
| Operating temperature range (°C) | -40 to 85 |
| SOIC (D) | 8 | 29.4 mm² 4.9 x 6 |
| VSSOP (DGK) | 8 | 14.7 mm² 3 x 4.9 |
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