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• 3 MHz–40 MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
• Capable to Drive Shielded Twisted-Pair Cable
• User Selectable Clock Edge for Parallel Data on both Transmitter and Receiver
• Internal DC Balancing Encode/Decode – Supports AC-Coupling Interface with no External Coding Required
• Individual Power-Down Controls for both Transmitter and Receiver
• Embedded Clock CDR (Clock and Data Recovery) on Receiver and no External Source of Reference Clock Needed
• All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
• LOCK Output Flag to Ensure Data Integrity at Receiver Side
• Balanced T_SETUP/T_HOLD Between RCLK and RDATA on Receiver Side
• PTO (Progressive Turn-On) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
• All LVCMOS inputs and control pins have internal pulldown
• On-Chip Filters for PLLs on Transmitter and Receiver
• Integrated 100Ω Input Termination on Receiver
• 4 mA Receiver Output Drive
• 48-Pin TQFP and 48-Pin WQFN Packages
• Pure CMOS .35 μm Process
• Power Supply Range 3.3V ± 10%
• Temperature Range −40°C to +85°C
• 8 kV HBM ESD Tolerance

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