h1_key

• 3 MHz–40 MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
• User Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver
• Internal DC Balancing Encode/Decode – Supports AC-Coupling Interface with No External Coding Required
• Individual Power-Down Controls for Both Transmitter and Receiver
• Embedded Clock CDR (Clock and Data Recovery) on Receiver and No External Source of Reference Clock Needed
• All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
• LOCK Output Flag to Ensure Data Integrity at Receiver Side
• Balanced T_SETUP/T_HOLD Between RCLK and RDATA on Receiver Side
• PTO (Progressive Turn-On) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
• All LVCMOS Inputs and Control Pins Have Internal Pulldown
• On-Chip Filters for PLLs on Transmitter and Receiver
• 48-Pin TQFP Package
• Pure CMOS .35 μm Process
• Power Supply Range 3.3V ± 10%
• Temperature Range 0°C to +70°C
• 8 kV HBM ESD Tolerance

All trademarks are the property of their respective owners.