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• No Special Start-up Sequence Required between Clock/Data and /PD Pins. Input Signal (Clock and Data) can be Applied Either Before or After the Device is Powered.
• Support Spread Spectrum Clocking up to 100KHz Frequency Modulation & Deviations of ±2.5% Center Spread or −5% Down Spread.
• "Input Clock Detection" Feature will Pull all LVDS Pairs to Logic Low when Input Clock is Missing and when /PD Pin is Logic High.
• 18 to 68 MHz Shift Clock Support
• Best–in–Class Set & Hold Times on TxINPUTs
• Tx Power Consumption < 130 mW (typ) @65MHz Grayscale
• 40% Less Power Dissipation than BiCMOS Alternatives
• Tx Power-Down Mode < 37μW (typ)
• Supports VGA, SVGA, XGA and Dual Pixel SXGA.
• Narrow Bus Reduces Cable Size and Cost
• Up to 1.3 Gbps Throughput
• Up to 170 Megabytes/sec Bandwidth
• 345 mV (typ) Swing LVDS Devices for Low EMI
• PLL Requires no External Components
• Compatible with TIA/EIA-644 LVDS Standard
• Low Profile 48-lead TSSOP Package
• Improved Replacement for:
  • SN75LVDS84, DS90CF363A

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