h1_key

• No special start-up sequence required between clock/data and /PD pins. Input signal (clock and data) can be applied either before or after the device is powered
• Support Spread Spectrum Clocking up to 100kHz frequency modulation and deviations of ±2.5% center spread or -5% down spread
• "Input Clock Detection" feature will pull all LVDS pairs to logic low when input clock is missing and when /PD pin is logic high
• 18 to 68 MHz shift clock support
• Best-in-Class Setup and Hold Times on TxINPUTs
• Tx power consumption < 130 mW (typ) at 65MHz Grayscale
• 40% Less Power Dissipation than BiCMOS Alternatives
• Tx Power-down mode < 60μW (typ)
• Supports VGA, SVGA, XGA and Dual Pixel SXGA.
• Narrow bus reduces cable size and cost
• Up to 1.8 Gbps throughput
• Up to 227 Megabytes/sec bandwidth
• 345 mV (typ) swing LVDS devices for low EMI
• PLL requires no external components
• Compatible with TIA/EIA-644 LVDS standard
• Low profile 56-lead TSSOP package
• Improved replacement for:
  • SN75LVDS83, DS90C383A

All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments. TRI-STATE is a trademark of Texas Instruments.