h1_key

TI(德州仪器) PCI2050B
德州仪器 (TI) 全系列产品在线购买
  • TI(德州仪器) PCI2050B
  • TI(德州仪器) PCI2050B
  • TI(德州仪器) PCI2050B
  • TI(德州仪器) PCI2050B
  • TI(德州仪器) PCI2050B
  • TI(德州仪器) PCI2050B
立即查看
您当前的位置: 首页 > 接口 > PCIe、SAS 和 SATA IC > PCI2050B
PCI2050B

PCI2050B

正在供货

PCI 至 PCI 桥接器

产品详情
  • 说明
  • 特性
  • 参数
  • 封装 | 引脚 | 尺寸

The Texas Instruments PCI2050B PCI-to-PCI bridge provides a high performance connection path between two peripheral component interconnect (PCI) buses operating at a maximum bus frequency of 66-MHz. Transactions occur between masters on one and targets on another PCI bus, and the PCI2050B bridge allows bridged transactions to occur concurrently on both buses. The bridge supports burst mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act independently.

The PCI2050B bridge is compliant with the PCI Local Bus Specification, and can be used to overcome the electrical loading limits of 10 devices per PCI bus and one PCI device per extension slot by creating hierarchical buses. The PCI2050B provides two-tier internal arbitration for up to nine secondary bus masters and may be implemented with an external bus arbiter.

The CompactPCI™ hot-swap extended PCI capability makes the PCI2050B bridge an ideal solution for multifunction compact PCI cards and adapting single function cards to hot-swap compliance.

The PCI2050B bridge is compliant with the PCI-to-PCI Bridge Specification (Revision 1.1). The PCI2050B bridge provides compliance for PCI Bus Power Management Interface Specification (Revision 1.1). The PCI2050B bridge has been designed to lead the industry in power conservation and data throughput. An advanced CMOS process achieves low system power consumption while operating at PCI clock rates up to 66-MHz.

  • Two 32-bit, 66-MHz PCI buses
  • 3.3-V core logic with universal PCI interfaces compatible
    with 3.3-V and 5-V PCI signaling environments
  • Internal two-tier arbitration for up to nine secondary
    bus masters and supports an external secondary bus arbiter
  • Ten secondary PCI clock outputs
  • Independent read and write buffers for each direction
  • Burst data transfers with pipeline architecture to maximize
    data throughput in both directions
  • Supports write combing for enhanced data throughput
  • Up to three delayed transactions in both directions
  • Supports the frame-to-frame delay of only four PCI clocks
    from one bus to another
  • Bus locking propagation
  • Predictable latency per PCI Local Bus Specification
  • Architecture configurable for PCI Bus Power Management
    Interface Specification
  • CompactPCI hot-swap functionality
  • Secondary bus is driven low during reset
  • VGA/palette memory and I/O decoding options
  • Advanced submicron, low-power CMOS technology
  • 208-terminal PDV, 208-terminal PPM, or 257-terminal
    MicroStar BGA™ package

TypeBridge
ProtocolsPCIe
ApplicationsPCIe
Number of channels2
Speed (max) (Gbps)0.066
Supply voltage (V)3.3, 5
RatingCatalog
Operating temperature range (°C)-40 to 85
LQFP (PDV)208784 mm² 28 x 28
NFBGA (ZWT)257256 mm² 16 x 16
产品购买
  • 商品型号
  • 封装
  • 工作温度
  • 包装
  • 价格
  • 现货库存
  • 操作
10s
温馨提示:
订单商品问题请移至我的售后服务提交售后申请,其他需投诉问题可移至我的投诉提交,我们将在第一时间给您答复
返回顶部