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• 12 to 85 MHz Shift Clock Support
• 50% Duty Cycle on Receiver Output Clock
• Low Power Consumption
• ±1V Common-mode Range (Around +1.2V)
• Narrow Bus Reduces Cable Size and Cost
• Up to 1.785 Gbps Throughput
• Up to 223 Mbytes/sec Bandwidth
• 345 mV (typ) Swing LVDS Devices for Low EMI
• PLL Requires No External Components
• Rising Edge Data Strobe
• Compatible with TIA/EIA-644 LVDS Standard
• Low Profile 48-Lead TSSOP Package

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