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TI(德州仪器) SN74LVCH16T245-EP
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  • TI(德州仪器) SN74LVCH16T245-EP
  • TI(德州仪器) SN74LVCH16T245-EP
  • TI(德州仪器) SN74LVCH16T245-EP
  • TI(德州仪器) SN74LVCH16T245-EP
  • TI(德州仪器) SN74LVCH16T245-EP
  • TI(德州仪器) SN74LVCH16T245-EP
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SN74LVCH16T245-EP

SN74LVCH16T245-EP

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具有可配置电压转换和三态输出的 16 位双电源总线收发器(增强型产品)

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  • 参数
  • 封装 | 引脚 | 尺寸

This 16-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.

The SN74LVCH16T245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA.

The SN74LVCH16T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, then all outputs are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

  • Control Inputs VIH/VIL Levels Are
    Referenced to VCCA Voltage
  • VCC Isolation Feature – If Either VCC
    Input Is at GND, All Outputs Are in the
    High-Impedance State
  • Overvoltage-Tolerant Inputs/Outputs Allow
    Mixed-Voltage-Mode Data Communications
  • Fully Configurable Dual-Rail Design Allows
    Each Port to Operate Over the Full 1.65-V to
    5.5-V Power-Supply Range
  • Bus Hold on Data Inputs Eliminates the Need
    for External Pullup/Pulldown Resistors
  • Ioff Supports Partial-Power-Down
    Mode Operation
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS

  • Controlled Baseline
  • One Assembly/Test Site
  • One Fabrication Site
  • Available in Military (–55°C/125°C)
    Temperature Range(1)
  • Extended Product Life Cycle
  • Extended Product-Change Notification
  • Product Traceability

(1) Custom temperature ranges available

Technology familyLVC
Bits (#)16
High input voltage (min) (V)1.08
High input voltage (max) (V)5.5
Vout (min) (V)1.65
Vout (max) (V)5.5
Data rate (max) (Mbps)200
IOH (max) (mA)-32
IOL (max) (mA)32
Supply current (max) (µA)30
FeaturesBus-hold, Output enable, Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation
Input typeStandard CMOS
Output type3-State, Balanced CMOS, Push-Pull
RatingHiRel Enhanced Product
Operating temperature range (°C)-55 to 125
TSSOP (DGG)48101.25 mm² 12.5 x 8.1
TVSOP (DGV)4862.08 mm² 9.7 x 6.4
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