The AUP family is TIs premier solution to the industrys low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see Figure 1 and Figure 2).
The SN74AUP2G125 is a dual bus buffer gate designed for 0.8-V to 3.6-V VCC operation. This device features dual line drivers with 3-state outputs. Each output is disabled when the corresponding output-enable (OE) input is high. This device has the input-disable feature, which allows floating input signals.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
NanoStar is a trademark of Texas Instruments
| Technology family | AUP |
| Supply voltage (min) (V) | 0.8 |
| Supply voltage (max) (V) | 3.6 |
| Number of channels | 2 |
| IOL (max) (mA) | 4 |
| Supply current (max) (µA) | 0.9 |
| IOH (max) (mA) | -4 |
| Input type | Standard CMOS |
| Output type | 3-State |
| Features | Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) |
| Rating | Catalog |
| Operating temperature range (°C) | -40 to 85 |
| DSBGA (YFP) | 8 | 1.8 mm² 1 x 1.8 |
| DSBGA (YZP) | 8 | 2.8125 mm² 2.25 x 1.25 |
| UQFN (RSE) | 8 | 2.25 mm² 1.5 x 1.5 |
| VSSOP (DCU) | 8 | 6.2 mm² 2 x 3.1 |
| X2SON (DQE) | 8 | 1.4 mm² 1.4 x 1 |