The SN74AUP1G125 bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high. This device has the input-disable feature, which allows floating input signals.
To ensure the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
| Technology family | AUP |
| Supply voltage (min) (V) | 0.8 |
| Supply voltage (max) (V) | 3.6 |
| Number of channels | 1 |
| IOL (max) (mA) | 4 |
| Supply current (max) (µA) | 0.9 |
| IOH (max) (mA) | -4 |
| Input type | Standard CMOS |
| Output type | 3-State |
| Features | Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) |
| Rating | Catalog |
| Operating temperature range (°C) | -40 to 85 |
| DSBGA (YFP) | 6 | 1.4000000000000001 mm² 1 x 1.4000000000000001 |
| DSBGA (YZP) | 5 | 2.1875 mm² 1.75 x 1.25 |
| SOT-23 (DBV) | 5 | 8.12 mm² 2.9 x 2.8 |
| SOT-5X3 (DRL) | 5 | 2.56 mm² 1.6 x 1.6 |
| SOT-SC70 (DCK) | 5 | 4.2 mm² 2 x 2.1 |
| USON (DRY) | 6 | 1.45 mm² 1.45 x 1 |
| X2SON (DPW) | 5 | 0.64 mm² 0.8 x 0.8 |
| X2SON (DSF) | 6 | 1 mm² 1 x 1 |
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