The AUP family is TIs premier solution to the industrys low-power needs in battery-powered portable applications. This family assures a very-low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, thus resulting in an increased battery life. The AUP devices also maintain excellent signal integrity.
The SN74AUP1G79 is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup-time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
The SN74AUP1G79 device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
| Number of channels | 1 |
| Technology family | AUP |
| Supply voltage (min) (V) | 0.8 |
| Supply voltage (max) (V) | 3.6 |
| Input type | Standard CMOS |
| Output type | Push-Pull |
| Clock frequency (max) (MHz) | 260 |
| IOL (max) (mA) | 4 |
| IOH (max) (mA) | -4 |
| Supply current (max) (µA) | 0.9 |
| Features | Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) |
| Operating temperature range (°C) | -40 to 85 |
| Rating | Catalog |
| SOT-23 (DBV) | 5 | 8.12 mm² 2.9 x 2.8 |
| SOT-5X3 (DRL) | 5 | 2.56 mm² 1.6 x 1.6 |
| SOT-SC70 (DCK) | 5 | 4.2 mm² 2 x 2.1 |
| USON (DRY) | 6 | 1.45 mm² 1.45 x 1 |
| X2SON (DPW) | 5 | 0.64 mm² 0.8 x 0.8 |
| X2SON (DSF) | 6 | 1 mm² 1 x 1 |