This octal buffer/driver is designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.
The SN74LV244AT is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
| Technology family | LV-AT |
| Supply voltage (min) (V) | 4.5 |
| Supply voltage (max) (V) | 5.5 |
| Number of channels | 8 |
| IOL (max) (mA) | 16 |
| Supply current (max) (µA) | 20 |
| IOH (max) (mA) | -16 |
| Input type | TTL-Compatible CMOS |
| Output type | 3-State |
| Features | Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) |
| Rating | Catalog |
| Operating temperature range (°C) | -40 to 85 |
| SOIC (DW) | 20 | 131.84 mm² 12.8 x 10.3 |
| SOP (NS) | 20 | 98.28 mm² 12.6 x 7.8 |
| TSSOP (PW) | 20 | 41.6 mm² 6.5 x 6.4 |
| VQFN (RGY) | 20 | 15.75 mm² 4.5 x 3.5 |
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