This single D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G175 device has an asynchronous clear (CLR) input. When CLR is high, data from the input pin (D) is transferred to the output pin (Q) on the clock's (CLK) rising edge. When CLR is low, Q is forced into the low state, regardless of the clock edge or data on D.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
| Number of channels | 1 |
| Technology family | LVC |
| Supply voltage (min) (V) | 1.65 |
| Supply voltage (max) (V) | 5.5 |
| Input type | Standard CMOS |
| Output type | Push-Pull |
| Clock frequency (max) (MHz) | 150 |
| IOL (max) (mA) | 32 |
| IOH (max) (mA) | -32 |
| Supply current (max) (µA) | 10 |
| Features | Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) |
| Operating temperature range (°C) | -40 to 125 |
| Rating | Catalog |
| DSBGA (YZP) | 6 | 2.1875 mm² 1.75 x 1.25 |
| SOT-23 (DBV) | 6 | 8.12 mm² 2.9 x 2.8 |
| SOT-SC70 (DCK) | 6 | 4.2 mm² 2 x 2.1 |
| USON (DRY) | 6 | 1.45 mm² 1.45 x 1 |
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