Each data selector/multiplexer contains inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate output-control inputs are provided for each of the two 4-line sections.
The 3-state outputs can interface with and drive data lines of bus-organized systems. With all but one of the common outputs disabled (in the high-impedance state), the low impedance of the single enabled output drives the bus line to a high or low logic level. Each output has its own output-enable (OE) input. The outputs are disabled when their respective OE is high.
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
| Technology family | HC |
| Function | Digital Multiplexer |
| Configuration | 4 |
| Number of channels | 2 |
| Operating temperature range (°C) | -40 to 125 |
| Rating | HiRel Enhanced Product |
| SOIC (D) | 16 | 59.4 mm² 9.9 x 6 |
关注公众号，优惠活动早知道！
Copyright ©2023 wlxmall.com万联芯城版权所有 | 电信与信息服务业务经营许可证100798号 | 粤ICP备14012234号 | 投诉建议
客服电话：4000-306-326 文明办网文明上网举报电话：010-82615762 违法不良信息举报中心
| * 我的问题/建议： | |
| * 联系电话： | |
| 上传图片（选填）： |
请您提交2M以内的jpg,gif,png格式文件 |
| 投诉订单号（选填）： | |
购物车中还没有商品，赶紧选购吧！
正在供货
加入购物车
