The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and can be used in conjunction with the clock enable (CE) input to cascade several stages. CE disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.
The device can drive up to ten low-power Schottky equivalent loads.
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
| Function | Counter |
| Bits (#) | 10 |
| Technology family | HC |
| Supply voltage (min) (V) | 2 |
| Supply voltage (max) (V) | 6 |
| Input type | Standard CMOS |
| Output type | Push-Pull |
| Features | Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode |
| Operating temperature range (°C) | -40 to 125 |
| Rating | HiRel Enhanced Product |
| SOIC (D) | 16 | 59.4 mm² 9.9 x 6 |
| TSSOP (PW) | 16 | 32 mm² 5 x 6.4 |
关注公众号，优惠活动早知道！
Copyright ©2023 wlxmall.com万联芯城版权所有 | 电信与信息服务业务经营许可证100798号 | 粤ICP备14012234号 | 投诉建议
客服电话：4000-306-326 文明办网文明上网举报电话：010-82615762 违法不良信息举报中心
| * 我的问题/建议： | |
| * 联系电话： | |
| 上传图片（选填）： |
请您提交2M以内的jpg,gif,png格式文件 |
| 投诉订单号（选填）： | |
购物车中还没有商品，赶紧选购吧！
正在供货
加入购物车
