This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
| Number of channels | 2 |
| Technology family | LVC |
| Supply voltage (min) (V) | 1.65 |
| Supply voltage (max) (V) | 5.5 |
| Input type | Standard CMOS |
| Output type | Push-Pull |
| Clock frequency (max) (MHz) | 150 |
| IOL (max) (mA) | 32 |
| IOH (max) (mA) | -32 |
| Supply current (max) (µA) | 5 |
| Features | Balanced outputs, Over-voltage tolerant inputs |
| Operating temperature range (°C) | -40 to 125 |
| Rating | Catalog |
| DSBGA (YZP) | 8 | 2.8125 mm² 2.25 x 1.25 |
| SSOP (DCT) | 8 | 11.8 mm² 2.95 x 4 |
| VSSOP (DCU) | 8 | 6.2 mm² 2 x 3.1 |
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