SN74AUC125系列介绍资料

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SN74AUC125

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具有三态输出的 4 通道、0.8V 至 2.7V 高速缓冲器

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This quadruple bus buffer gate is designed for 0.8-V to 2.7-V V_CC operation, but is designed specifically for 1.6-V to 1.95-V V_CCoperation.

The SN74AUC125 contains four independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
I_off Supports Partial-Power-Down Mode Operation
Sub-1-V Operable
Max t_pd of 2.1 ns at 1.8 V
Low Power Consumption, 10-µA Max I_CC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1500-V Charged-Device Model (C101)

Technology family	AUC
Supply voltage (min) (V)	0.8
Supply voltage (max) (V)	2.7
Number of channels	4
IOL (max) (mA)	9
Supply current (max) (µA)	10
IOH (max) (mA)	-9
Input type	Standard CMOS
Output type	3-State
Features	Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)
Rating	Catalog
Operating temperature range (°C)	-40 to 85

VQFN (RGY)

12.25 mm² 3.5 x 3.5

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SN74AUC125

具有三态输出的 4 通道、0.8V 至 2.7V 高速缓冲器

4000-306-326