The SN74AHC125 is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
EPIC is a trademark of Texas Instruments.
| Technology family | AHC |
| Supply voltage (min) (V) | 2 |
| Supply voltage (max) (V) | 5.5 |
| Number of channels | 4 |
| IOL (max) (mA) | 50 |
| Supply current (max) (µA) | 40 |
| IOH (max) (mA) | -50 |
| Input type | Standard CMOS |
| Output type | 3-State |
| Features | Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) |
| Rating | HiRel Enhanced Product |
| Operating temperature range (°C) | -55 to 125 |
| SOIC (D) | 14 | 51.9 mm² 8.65 x 6 |
| TSSOP (PW) | 14 | 32 mm² 5 x 6.4 |
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