This octal buffer/driver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.
The SN74AUC240 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
This device is organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
| Technology family | AUC |
| Supply voltage (min) (V) | 0.8 |
| Supply voltage (max) (V) | 2.7 |
| Number of channels | 8 |
| IOL (max) (mA) | 9 |
| IOH (max) (mA) | -9 |
| Supply current (max) (µA) | 20 |
| Input type | Standard CMOS |
| Output type | 3-State |
| Features | Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) |
| Rating | Catalog |
| Operating temperature range (°C) | -40 to 85 |
| VQFN (RGY) | 20 | 15.75 mm² 4.5 x 3.5 |
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