The SN74LVC2G125 device is a dual bus buffer gate, designed for 1.65-V to 5.5-V VCC operation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high.
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To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
| Technology family | LVC |
| Supply voltage (min) (V) | 1.65 |
| Supply voltage (max) (V) | 5.5 |
| Number of channels | 2 |
| IOL (max) (mA) | 32 |
| Supply current (max) (µA) | 10 |
| IOH (max) (mA) | -32 |
| Input type | Standard CMOS |
| Output type | 3-State |
| Features | Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) |
| Rating | Catalog |
| Operating temperature range (°C) | -40 to 125 |
| DSBGA (YZP) | 8 | 2.8125 mm² 2.25 x 1.25 |
| SSOP (DCT) | 8 | 11.8 mm² 2.95 x 4 |
| VSSOP (DCU) | 8 | 6.2 mm² 2 x 3.1 |
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