SN74LV20A系列介绍资料

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SN74LV20A

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2 通道、4 输入、2V 至 5.5V 与非门

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These dual 4-input positive-NAND gates are designed for 2-V to 5.5-V V_CC operation.

The 'LV20A devices perform the Boolean function Y = (A • B • C • D) or Y = A + B + C + D in positive logic.

These devices are fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

2-V to 5.5-V V_CC Operation
Max t_pd of 6 ns at 5 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>>2.3 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Technology family	LV-A
Supply voltage (min) (V)	2
Supply voltage (max) (V)	5.5
Number of channels	2
Inputs per channel	4
IOL (max) (mA)	12
IOH (max) (mA)	-12
Input type	Standard CMOS
Output type	Push-Pull
Features	Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)
Data rate (max) (Mbps)	70
Rating	Catalog
Operating temperature range (°C)	-40 to 85

SOIC (D)	14	51.9 mm² 8.65 x 6
SOP (NS)	14	79.56 mm² 10.2 x 7.8
SSOP (DB)	14	48.36 mm² 6.2 x 7.8
TSSOP (PW)	14	32 mm² 5 x 6.4
TVSOP (DGV)	14	23.04 mm² 3.6 x 6.4

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SN74LV20A

2 通道、4 输入、2V 至 5.5V 与非门

4000-306-326