The x92FCT273T devices consist of eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered-clock (CP) and master-reset (MR) inputs load and reset all flip-flops simultaneously. These devices are edge-triggered registers. The state of each D input (one setup time before the low-to-high clock transition) is transferred to the corresponding flip-flopx92s Q output. All outputs are forced low by a low logic level on the MR input.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
| Number of channels | 8 |
| Technology family | FCT |
| Supply voltage (min) (V) | 4.5 |
| Supply voltage (max) (V) | 5.5 |
| Input type | TTL-Compatible CMOS |
| Output type | Push-Pull |
| Clock frequency (max) (MHz) | 70 |
| IOL (max) (mA) | 64 |
| IOH (max) (mA) | -32 |
| Supply current (max) (µA) | 200 |
| Features | High speed (tpd 10-50ns) |
| Operating temperature range (°C) | -55 to 125 |
| Rating | Military |
| CDIP (J) | 20 | 167.464 mm² 24.2 x 6.92 |
| LCCC (FK) | 20 | 79.0321 mm² 8.89 x 8.89 |
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