CD54HCT75系列介绍资料

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CD54HCT75

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高速 CMOS 逻辑双路 2 位双稳态透明锁存器

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The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E and 2E) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E and 2E) is LOW the output is not affected.

True and Complementary Outputs
Buffered Inputs and Outputs
Fanout (Over Temperature Range)
- Standard Outputs...10 LSTTL Loads
- Bus Driver Outputs...15 LSTTL Loads
Wide Operating Temperature Range . . . –55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l 1µA at V_OL, V_OH

Data sheet acquired from Harris Semiconductor

Number of channels	4
Technology family	HCT
Supply voltage (min) (V)	4.5
Supply voltage (max) (V)	5.5
Input type	TTL-Compatible CMOS
Output type	CMOS
Clock frequency (max) (MHz)	25
IOL (max) (mA)	4
IOH (max) (mA)	-4
Supply current (max) (µA)	80
Features	Partial power down (Ioff), Standard speed (tpd > 50ns), Very high speed (tpd 5-10ns)
Operating temperature range (°C)	-55 to 125
Rating	Military

CDIP (J)

135.3552 mm² 19.56 x 6.92

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CD54HCT75

高速 CMOS 逻辑双路 2 位双稳态透明锁存器

4000-306-326