The 'HC590A devices contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features direct clear (CCLR) and count-enable (CCKEN) inputs. A ripple-carry output (RCO) is provided for cascading. Expansion is accomplished easily for two stages by connecting RCO of the first stage to CCKEN of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage to the counter clock (CCLK) input of the following stage.
CCLK and the register clock (RCLK) inputs are positive-edge triggered. If both clocks are connected together, the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock enable.
| Function | Counter |
| Bits (#) | 8 |
| Technology family | HC |
| Supply voltage (min) (V) | 2 |
| Supply voltage (max) (V) | 6 |
| Input type | Standard CMOS |
| Output type | 3-State |
| Features | Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode |
| Operating temperature range (°C) | -55 to 125 |
| Rating | Military |
| CDIP (J) | 16 | 135.3552 mm² 19.56 x 6.92 |
| CFP (W) | 16 | 69.319 mm² 10.3 x 6.73 |
| LCCC (FK) | 20 | 79.0321 mm² 8.89 x 8.89 |
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