The ’ACT74 dual positive-edge-triggered devices are D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.
| Number of channels | 2 |
| Technology family | ACT |
| Supply voltage (min) (V) | 4.5 |
| Supply voltage (max) (V) | 5.5 |
| Input type | TTL-Compatible CMOS |
| Output type | Push-Pull |
| Clock frequency (max) (MHz) | 100 |
| IOL (max) (mA) | 24 |
| IOH (max) (mA) | -24 |
| Supply current (max) (µA) | 20 |
| Features | Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns) |
| Operating temperature range (°C) | -55 to 125 |
| Rating | Military |
| CDIP (J) | 14 | 130.4652 mm² 19.56 x 6.67 |
| CFP (W) | 14 | 58.023 mm² 9.21 x 6.3 |
| LCCC (FK) | 20 | 79.0321 mm² 8.89 x 8.89 |
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