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TI(德州仪器) SN54LS75
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  • TI(德州仪器) SN54LS75
  • TI(德州仪器) SN54LS75
  • TI(德州仪器) SN54LS75
  • TI(德州仪器) SN54LS75
  • TI(德州仪器) SN54LS75
  • TI(德州仪器) SN54LS75
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SN54LS75

SN54LS75

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4 位双稳态锁存器

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These latches are ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable (C) is high and the Q output will follow the data input as long as the enable remains high. When the enable goes low, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the enable is permitted to go high.

The '75 and 'LS75 feature complementary Q and Q outputs from a 4-bit latch, and are available in various 16-pin packages. For higher component density applications, the '77 and 'LS77 4-bit latches are available in 14-pin flat packages.

These circuits are completely compatible with all popular TTL families. All inputs are diode-clamped to minimize transmission-line effects and simplify system design. Series 54 and 54LS devices are characterized for operation over the full military temperature range of -55°C to 125°C; Series 74, and 74LS devices are characterized for operation from 0°C to 70°C.

 

Number of channels4
Technology familyLS
Supply voltage (min) (V)4.75
Supply voltage (max) (V)5.25
Input typeBipolar
Output typeTTL
Clock frequency (max) (MHz)35
IOL (max) (mA)8
IOH (max) (mA)-0.4
Supply current (max) (µA)46000
FeaturesVery high speed (tpd 5-10ns)
Operating temperature range (°C)-55 to 125
RatingMilitary
CDIP (J)16135.3552 mm² 19.56 x 6.92
CFP (W)1669.319 mm² 10.3 x 6.73
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