SN54LVC373A系列介绍资料

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SN54LVC373A

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具有三态输出的八路透明 D 类锁存器

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The SN54LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V V_CC operation, and the SN74LVC373A octal transparent D-type latch is designed for 1.65-V to 3.6-V V_CC operation.

For all available packages, see the orderable addendum at the end of the data sheet.

Operate From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t_pd of 6.8 ns at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
Supports Mixed-Mode Signal Operation
on All Ports
(5-V Input/Output Voltage With 3.3-V V_CC)
I_off Supports Live-Insertion, Partial-Power-Down Mode,
and Back-Drive Protection
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
On Products Compliant to MIL-PRF-38535, All
Parameters Are Tested Unless Otherwise Noted.
On All Other Products, Production Processing
Does Not Necessarily Include Testing of All
Parameters.

Number of channels	8
Technology family	LVC
Supply voltage (min) (V)	2
Supply voltage (max) (V)	3.6
Input type	Standard CMOS
Output type	3-State
Clock frequency (max) (MHz)	100
IOL (max) (mA)	24
IOH (max) (mA)	-24
Supply current (max) (µA)	10
Features	Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)
Operating temperature range (°C)	-55 to 125
Rating	Military

CDIP (J)	20	167.464 mm² 24.2 x 6.92
CFP (W)	20	90.5828 mm² 13.09 x 6.92
LCCC (FK)	20	79.0321 mm² 8.89 x 8.89

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SN54LVC373A

具有三态输出的八路透明 D 类锁存器

4000-306-326