The ’LV126A quadruple bus buffer gates are designed for 2-V to 5.5-V VCC operation.
These quadruple bus buffer gates are designed for 2-V to 5.5-V VCC operation.
The ’LV126A devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
| Technology family | LV-A |
| Supply voltage (min) (V) | 2 |
| Supply voltage (max) (V) | 5.5 |
| Number of channels | 4 |
| IOL (max) (mA) | 16 |
| Supply current (max) (µA) | 20 |
| IOH (max) (mA) | -16 |
| Input type | Standard CMOS |
| Output type | 3-State |
| Features | Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) |
| Rating | Catalog |
| Operating temperature range (°C) | -40 to 125 |
| SOIC (D) | 14 | 51.9 mm² 8.65 x 6 |
| SOP (NS) | 14 | 79.56 mm² 10.2 x 7.8 |
| SSOP (DB) | 14 | 48.36 mm² 6.2 x 7.8 |
| TSSOP (PW) | 14 | 32 mm² 5 x 6.4 |
| TVSOP (DGV) | 14 | 23.04 mm² 3.6 x 6.4 |
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