CD4043B系列介绍资料

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CD4043B

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具有三态输出的 CMOS 四路或非 R/S 锁存器

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CD4043B types are quad cross-coupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.

The CD4043B and CD4044B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline package (D, DR, DT, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

3-state outputs with common output ENABLE
Separate SET and RESET inputs for each latch
NOR and NAND configurations
5-V, 10-V, and 15-V parametric ratings
Standardized symmetrical output characteristics
100% tested for quiescent current at 20 V
Maximum input current of 1 µA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
- 1 V at V_DD = 5 V
- 2 V at V_DD = 10 V
- 2.5 V at V_DD = 15 V
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
Applications
- Holding register in multi-register system
- Four bits of independent storage with output ENABLE
- Strobed register
- General digital logic
- CD4043B for positive logic systems
- CD4044B for negative logic systems

Data sheet acquired from Harris Semiconductor

Function	RS latch
Number of channels	4
Technology family	CD4000
Supply voltage (min) (V)	3
Supply voltage (max) (V)	18
Input type	Standard CMOS
Output type	3-State
Data rate (max) (Mbps)	16
IOL (max) (mA)	2.4
IOH (max) (mA)	-2.4
Features	High speed (tpd 10-50ns), Partial power down (Ioff), Standard speed (tpd > 50ns)
Operating temperature range (°C)	-55 to 125
Rating	Catalog

PDIP (N)	16	181.42 mm² 19.3 x 9.4
SOIC (D)	16	59.4 mm² 9.9 x 6
SOIC (DW)	16	106.09 mm² 10.3 x 10.3
SOP (NS)	16	79.56 mm² 10.2 x 7.8
TSSOP (PW)	16	32 mm² 5 x 6.4

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CD4043B

具有三态输出的 CMOS 四路或非 R/S 锁存器

4000-306-326