h1_key

TI(德州仪器) CD4025B
德州仪器 (TI) 全系列产品在线购买
  • TI(德州仪器) CD4025B
  • TI(德州仪器) CD4025B
  • TI(德州仪器) CD4025B
  • TI(德州仪器) CD4025B
  • TI(德州仪器) CD4025B
  • TI(德州仪器) CD4025B
立即查看
您当前的位置: 首页 > 逻辑和电压转换 > 逻辑门 > 或非门 > CD4025B
CD4025B

CD4025B

正在供货

3 通道、3 输入、3V 至 18V 或非门

产品详情
  • 说明
  • 特性
  • 参数
  • 封装 | 引脚 | 尺寸

CD4001B, CD4002B, and CD4025B NOR gates provide the system designer with direct implementation of the NOR function and supplement the existing family of CMOS gates. All inputs and outputs are buffered.

The CD4001B, CD4002B, and CD4025B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

  • Propagation delay time = 60 ns (typ.) at CL = 50 pF, VDD = 10 V
  • Buffered inputs and outputs
  • Standardized symmetrical output characteristics
  • 100% tested for maximum quiescent current at 20 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (over full package temperature range):
         1 V at VDD = 5 V
         2 V at VDD = 10 V
      2.5 V at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor

Technology familyCD4000
Number of channels3
Supply voltage (min) (V)3
Supply voltage (max) (V)18
Inputs per channel3
IOL (max) (mA)6.8
IOH (max) (mA)-6.8
Output typePush-Pull
Input typeStandard CMOS
FeaturesStandard speed (tpd > 50ns)
Data rate (max) (Mbps)8
RatingCatalog
Operating temperature range (°C)-55 to 125
PDIP (N)14181.42 mm² 19.3 x 9.4
SOIC (D)1451.9 mm² 8.65 x 6
SOP (NS)1479.56 mm² 10.2 x 7.8
TSSOP (PW)1432 mm² 5 x 6.4
产品购买
  • 商品型号
  • 封装
  • 工作温度
  • 包装
  • 价格
  • 现货库存
  • 操作
10s
温馨提示:
订单商品问题请移至我的售后服务提交售后申请,其他需投诉问题可移至我的投诉提交,我们将在第一时间给您答复
返回顶部