CD74HC107系列介绍资料

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CD74HC107

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具有复位功能的高速 CMOS 逻辑双通道下降沿 J-K 触发器

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The ’HC107 and ’HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.

These flip-flops have independent J, K, Reset and Clock inputs and Q and Q outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input.

This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits.

The HCT logic family is functionally as well as pin compatible with the standard LS family.

Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times
Asynchronous Reset
Complementary Outputs
Buffered Inputs
Typical f_MAX = 60MHz at V_CC = 5V, C_L = 15pF, T_A = 25°C
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l 1µA at V_OL, V_OH

Number of channels	2
Technology family	HC
Supply voltage (min) (V)	2
Supply voltage (max) (V)	6
Input type	LVTTL/CMOS
Output type	Push-Pull
Clock frequency (MHz)	24
Supply current (max) (µA)	40
IOL (max) (mA)	6
IOH (max) (mA)	-6
Features	Balanced outputs, Clear, High speed (tpd 10-50ns), Negative edge triggered, Positive input clamp diode
Operating temperature range (°C)	-55 to 125
Rating	Catalog

PDIP (N)	14	181.42 mm² 19.3 x 9.4
SOIC (D)	14	51.9 mm² 8.65 x 6

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CD74HC107

具有复位功能的高速 CMOS 逻辑双通道下降沿 J-K 触发器

4000-306-326