These devices are positive-edge-triggered D-type
flip-flops with a direct clear (CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
| Number of channels | 8 |
| Technology family | AHC |
| Supply voltage (min) (V) | 2 |
| Supply voltage (max) (V) | 5.5 |
| Input type | Standard CMOS |
| Output type | Push-Pull |
| Clock frequency (max) (MHz) | 110 |
| IOL (max) (mA) | 8 |
| IOH (max) (mA) | -8 |
| Supply current (max) (µA) | 40 |
| Features | Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs |
| Operating temperature range (°C) | -40 to 125 |
| Rating | Catalog |
| PDIP (N) | 20 | 228.702 mm² 24.33 x 9.4 |
| SOIC (DW) | 20 | 131.84 mm² 12.8 x 10.3 |
| SOP (NS) | 20 | 98.28 mm² 12.6 x 7.8 |
| SSOP (DB) | 20 | 56.16 mm² 7.2 x 7.8 |
| TSSOP (PW) | 20 | 41.6 mm² 6.5 x 6.4 |
| TVSOP (DGV) | 20 | 32 mm² 5 x 6.4 |
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