These decimal decoders consist of eight inverters and ten 4-input NAND gates. The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of valid input logic ensures that all inputs remain off for all invalid input conditions.
| Technology family | HC |
| Number of channels | 1 |
| Operating temperature range (°C) | -40 to 85 |
| Rating | Catalog |
| Supply current (max) (µA) | 80 |
| PDIP (N) | 16 | 181.42 mm² 19.3 x 9.4 |
| SOIC (D) | 16 | 59.4 mm² 9.9 x 6 |