CD4019B types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single-input OR gate. Selection is accomplished by control bits Ka and Kb. In addition to selection of either channel A or channel B information, the control bits can be applied simultaneously to accomplish the logical A + B function.
The CD4019B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
| Technology family | CD4000 |
| Supply voltage (min) (V) | 3 |
| Supply voltage (max) (V) | 18 |
| Number of channels | 4 |
| Inputs per channel | 4 |
| IOL (max) (mA) | 6.8 |
| IOH (max) (mA) | -6.8 |
| Input type | Standard CMOS |
| Output type | Push-Pull |
| Features | Standard speed (tpd > 50ns) |
| Data rate (max) (Mbps) | 8 |
| Rating | Catalog |
| Operating temperature range (°C) | -55 to 125 |
| PDIP (N) | 16 | 181.42 mm² 19.3 x 9.4 |
| SOIC (D) | 16 | 59.4 mm² 9.9 x 6 |
| SOP (NS) | 16 | 79.56 mm² 10.2 x 7.8 |
| TSSOP (PW) | 16 | 32 mm² 5 x 6.4 |
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