The SN74AHC595 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage registers. The shift register has a direct overriding clear (SRCLR) input, a serial (SER) input, and a serial output for cascading. When the output-enable (OE) input is high, all outputs except QH′ are in the high-impedance state.
| Configuration | Serial-in, Parallel-out |
| Bits (#) | 8 |
| Technology family | AHC |
| Supply voltage (min) (V) | 2 |
| Supply voltage (max) (V) | 5.5 |
| Input type | Standard CMOS |
| Output type | 3-State |
| Clock frequency (MHz) | 115 |
| IOL (max) (mA) | 8 |
| IOH (max) (mA) | -8 |
| Supply current (max) (µA) | 40 |
| Features | Balanced outputs, Output register, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) |
| Operating temperature range (°C) | -40 to 125 |
| Rating | Catalog |
| PDIP (N) | 16 | 181.42 mm² 19.3 x 9.4 |
| SOIC (D) | 16 | 59.4 mm² 9.9 x 6 |
| SSOP (DB) | 16 | 48.36 mm² 6.2 x 7.8 |
| TSSOP (PW) | 16 | 32 mm² 5 x 6.4 |
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