The SN54LVCH244A octal buffer/line driver is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVCH244A octal buffer/line driver is designed for 1.65-V to 3.6-V VCC operation.
These devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low, these devices pass data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
| Technology family | LVC |
| Supply voltage (min) (V) | 1.65 |
| Supply voltage (max) (V) | 3.6 |
| Number of channels | 8 |
| IOL (max) (mA) | 24 |
| Supply current (max) (µA) | 10 |
| IOH (max) (mA) | -24 |
| Input type | Standard CMOS |
| Output type | 3-State |
| Features | Balanced outputs, Bus-hold, Very high speed (tpd 5-10ns) |
| Rating | Catalog |
| Operating temperature range (°C) | -40 to 85 |
| SOIC (DW) | 20 | 131.84 mm² 12.8 x 10.3 |
| SOP (NS) | 20 | 98.28 mm² 12.6 x 7.8 |
| SSOP (DB) | 20 | 56.16 mm² 7.2 x 7.8 |
| SSOP (DBQ) | 20 | 51.9 mm² 8.65 x 6 |
| TSSOP (PW) | 20 | 41.6 mm² 6.5 x 6.4 |
| TVSOP (DGV) | 20 | 32 mm² 5 x 6.4 |
| VQFN (RGY) | 20 | 15.75 mm² 4.5 x 3.5 |