CD40174B系列介绍资料

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CD40174B

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CMOS 六路 D 类触发器

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Cd40174B consists of six identical ’D’-type flip-flops having independent DATA inputs. The CLOCK and CLEAR inputs are common to all six units. Data are transferred to the Q outputs on the positive-going transition of the clock pulse. All sic flip-flops are simultaneously reset by a low level on the CLEAR input.

The CD40174B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

5-V, 10-V, and 15-V parametric ratings
Standardized, symmetrical output characteristics
100% tested for quiescent current at 20 V
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (full package-temperature range) =
        1 V at V_DD = 5 V
        2 V at V_DD = 10 V
     2.5 V at V_DD = 15 V
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
Applications:
- Shift Registers
- Buffer/Storage Registers
- Pattern Generators

Number of channels	6
Technology family	CD4000
Supply voltage (min) (V)	3
Supply voltage (max) (V)	18
Input type	Standard CMOS
Output type	Push-Pull
Clock frequency (max) (MHz)	8
IOL (max) (mA)	6.8
IOH (max) (mA)	-6.8
Supply current (max) (µA)	600
Features	Balanced outputs, Positive input clamp diode, Standard speed (tpd > 50ns)
Operating temperature range (°C)	-55 to 125
Rating	Catalog

PDIP (N)	16	181.42 mm² 19.3 x 9.4
SOIC (D)	16	59.4 mm² 9.9 x 6
SOP (NS)	16	79.56 mm² 10.2 x 7.8
TSSOP (PW)	16	32 mm² 5 x 6.4

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CD40174B

CMOS 六路 D 类触发器

4000-306-326