CD74HCT597系列介绍资料

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CD74HCT597

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具有输入存储的高速 CMOS 逻辑 8 位移位寄存器

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The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL is high.

Buffered Inputs
Asynchronous Parallel Load
Fanout (Over Temperature Range)
- Standard Outputs...10 LSTTL Loads
- Bus Driver Outputs...15 LSTTL Loads
Wide Operating Temperature Range... –55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH

Data sheet acquired from Harris Semiconductor

Configuration	Parallel-in, Serial-out
Bits (#)	8
Technology family	HCT
Supply voltage (min) (V)	4.5
Supply voltage (max) (V)	5.5
Input type	TTL-Compatible CMOS
Output type	Push-Pull
Clock frequency (MHz)	24
IOL (max) (mA)	4
IOH (max) (mA)	-4
Supply current (max) (µA)	160
Features	Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode
Operating temperature range (°C)	-55 to 125
Rating	Catalog

PDIP (N)	16	181.42 mm² 19.3 x 9.4
SOIC (D)	16	59.4 mm² 9.9 x 6

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CD74HCT597

具有输入存储的高速 CMOS 逻辑 8 位移位寄存器

4000-306-326