The HC75 and HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E and 2E) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E and 2E) is LOW the output is not affected.
Data sheet acquired from Harris Semiconductor
| Number of channels | 4 |
| Technology family | HC |
| Supply voltage (min) (V) | 2 |
| Supply voltage (max) (V) | 6 |
| Input type | Standard CMOS |
| Output type | CMOS |
| Clock frequency (max) (MHz) | 28 |
| IOL (max) (mA) | 5.2 |
| IOH (max) (mA) | -5.2 |
| Supply current (max) (µA) | 80 |
| Features | High speed (tpd 10-50ns) |
| Operating temperature range (°C) | -55 to 125 |
| Rating | Catalog |
| PDIP (N) | 16 | 181.42 mm² 19.3 x 9.4 |
| SOIC (D) | 16 | 59.4 mm² 9.9 x 6 |
| TSSOP (PW) | 16 | 32 mm² 5 x 6.4 |