CD4521B consists of an oscillator section and 24 ripple-carry binary counter stages. The oscillator configuration (using IN1) allows design of either RC or crystal oscillator circuits. IN1 should be tied either HIGH or LOW when not in use. A HIGH on the RESET causes the counter to go to the all-0’s state and disables the oscillator. The count is advanced on the negative transition of IN1 (and IN2). A time-saving test mode is described in the Functional Test Sequence Table and in Fig. 6.
The CD4521B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
Data sheet acquired from Harris Semiconductor
| Function | Frequency divider |
| Bits (#) | 4 |
| Technology family | CD4000 |
| Supply voltage (min) (V) | 3 |
| Supply voltage (max) (V) | 18 |
| Input type | Standard CMOS |
| Output type | Push-Pull |
| Features | Partial power down (Ioff), Standard speed (tpd > 50ns) |
| Operating temperature range (°C) | -55 to 125 |
| Rating | Catalog |
| PDIP (N) | 16 | 181.42 mm² 19.3 x 9.4 |
| SOIC (D) | 16 | 59.4 mm² 9.9 x 6 |
| SOP (NS) | 16 | 79.56 mm² 10.2 x 7.8 |
| TSSOP (PW) | 16 | 32 mm² 5 x 6.4 |
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